Timing Extensions of STG Model and a Method to Simulate Timed STG Behavior in VHDL Environment
نویسندگان
چکیده
This paper includes an overview of the Signal Transition Graph (STG) model extensions that makes it possible to specify switching and signal propagation delays in an STG. The correspondence of the STG timing models to the implementation by asynchronous circuit is considered. A method to simulate the behavior speci ed by consistent and bounded timed STG in VHDL environment is proposed. For illustration we present a possible use of the VHDL-based STG representation in asynchronous circuits design.
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Timing Extensions and Simulation
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